1. Field of the Invention
The present invention relates to a technique for measuring the propagation delay of a transmission system, and more specifically to an apparatus and method for accurately measuring the transmission delay time of a signal propagation path between printed circuit boards by efficiently extracting a significantly attenuated high-speed broadband signal at the receiving point of the path. The present invention is particularly useful for a transmission link that transports high-speed broadband signals, such as rectangular pulses at frequencies higher than 100 MHz.
2. Description of the Related Art
The recent tendency toward using high-speed broadband signals has created a need for a precision measurement of their propagation delay time from output ports of an integrated circuit chip on a first printed circuit board to input ports of an integrated circuit chip on a second printed circuit board. The measured delay time data is used to precisely align delay timings between chip-to-chip parallel transmission channels for canceling inter-channel crosstalk. Two methods are currently available for determining the propagation delays. In one method, a sampling oscilloscope is used to directly evaluate time-domain responses (waveforms). According to the other method that is shown and described in Japanese Patent Publication 2004-104235, a network analyzer is used to calculate the inverse Fourier transform of the frequency-domain response characteristic of a transmission channel. Based on the result of this calculation, the network analyzer calculates the delay time of the channel.
If the transmission channel is designed to carry a broadband signal, the transmitted signal would be severely weakened by the inherent high-frequency loss of the transmission channel, so that it reduces significantly to a low level at the receive end of the channel in comparison with the level of random noise introduced to the channel.
If an oscilloscope were used to measure the delay time of a broadband signal on a noisy transmission medium it is necessary to suppress the noise component of the received signal. In order to suppress the random noise of a transmission channel, a test signal is transmitted at periodic intervals over the channel. To increase the signal-to-noise ratio at the receive end, the received signal is sampled at intervals, and the sample values are averaged over time. Since the number of samples necessary to achieve a desired signal-to-noise ratio depends on the level of the received signal, it is necessary to continue reception for a long period of time until a sufficient number of samples are obtained.
If the transmission delay time of a received signal were determined based on the frequency-domain response of the received signal, precision calibration is necessary to measure the frequency-domain response using a network analyzer. This involves the use of a number of standard blank circuit boards to perform calibration in different calibration modes, including open-circuit, loaded-circuit, short-circuit and through-circuit modes. After calibrations are performed for all modes, a pair of blank boards is used to measure the delay time of the transmission channel between them. If precision measurement of the delay time between two IC chips is required, a number of blank circuit boards must be prepared for each printed circuit board under test to perform calibration in open-circuit, loaded-circuit, short-circuit and through-circuit modes.
More specifically, as shown in FIG. 10, for each pair of printed circuit boards to be tested, there are provided a pair of blank circuit boards 401 and 405 to perform open-circuit calibration a pair of blank circuit boards 402 and 406 for load-circuit calibration, a pair of blank circuit boards 403 and 407 for short-circuit calibration, and a blank circuit board 404 for through-circuit calibration. Each blank circuit board is a non-printed circuit board, which is substantially similar in size and shape to, and is formed of the same material as, the tested printed circuit board and is provided with at least one connector to which a different circuit element is attached corresponding to each calibration mode. In the case of the open-circuit calibration, an etched short surface line 421 is attached to the connector 411 to simulate an open circuit. In the case of the loaded-circuit calibration, the connector 412 is connected by an etched short surface line 422 to a 50-ohm termination resistor 423 to serve as a load. In the short-circuit calibration boards 403, 407, the connector 413 is grounded through an etched short surface line 424. In the through-circuit calibration board 404, an etched short surface line 425 is used to connect connectors 414 and 415 to each other. To perform a frequency-domain response calibration, the connectors of each pair of blank circuit boards are connected to the ports 431 and 432 of a network analyzer 430 by cables shown in the dotted lines.
As shown in FIG. 11, when all calibrations are performed, a pair of test boards 502 and 512 is further prepared if it is desired to accurately determine the transmission delay time based on a measured frequency-domain response characteristic of a frequency-domain response test section 500 between two printed circuit boards. Test board 502 is provided with a PCB connector 501 with an input port 503 of the test section 500, the input port 503 being attached through etched lines 504 on the board 502 to a PCB connector 505. Likewise, the test board 512 is provided with a connector 513 with an output port 511 of the test section 500, the port 511 being attached through etched lines 510 to a PCB connector 509. Coaxial cable 507 is connected between the PCB connectors 505 and 509. Connectors 501 and 513 are fitted with ports 526 and 528, respectively, for connection to the network analyzer 430.
Network analyzer 430 has its output port 431 connected to the port 526 using an extension cable 517 and has its input port 432 connected to the port 528 using an extension cable 519. A frequency-domain test signal is transmitted from the output port 503 through the test section 500 to the input port 511.